@@ -3440,3 +3440,81 @@ define i1 @val_is_aligend_pred_mismatch(i32 %num) {
34403440 %_0 = icmp sge i32 %num.masked , %num
34413441 ret i1 %_0
34423442}
3443+
3444+ define i1 @icmp_samesign_with_nsw_add (i32 %arg0 ) {
3445+ ; CHECK-LABEL: @icmp_samesign_with_nsw_add(
3446+ ; CHECK-NEXT: entry:
3447+ ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[ARG0:%.*]], -26
3448+ ; CHECK-NEXT: [[V1:%.*]] = icmp ult i32 [[TMP0]], -8
3449+ ; CHECK-NEXT: ret i1 [[V1]]
3450+ ;
3451+ entry:
3452+ %v0 = add nsw i32 %arg0 , -18
3453+ %v1 = icmp samesign ugt i32 %v0 , 7
3454+ ret i1 %v1
3455+ }
3456+
3457+ ; Shouldn't fire since -124 - 12 causes signed overflow
3458+ define i1 @icmp_samesign_with_nsw_add_no_fire (i8 %arg0 ) {
3459+ ; CHECK-LABEL: @icmp_samesign_with_nsw_add_no_fire(
3460+ ; CHECK-NEXT: entry:
3461+ ; CHECK-NEXT: [[TMP0:%.*]] = add i8 [[ARG0:%.*]], -121
3462+ ; CHECK-NEXT: [[V1:%.*]] = icmp ult i8 [[TMP0]], 123
3463+ ; CHECK-NEXT: ret i1 [[V1]]
3464+ ;
3465+ entry:
3466+ %v0 = add nsw i8 %arg0 , 12
3467+ %v1 = icmp samesign ugt i8 %v0 , -124
3468+ ret i1 %v1
3469+ }
3470+
3471+ define i1 @icmp_with_nuw_add (i32 %arg0 ) {
3472+ ; CHECK-LABEL: @icmp_with_nuw_add(
3473+ ; CHECK-NEXT: entry:
3474+ ; CHECK-NEXT: [[V1:%.*]] = icmp ugt i32 [[ARG0:%.*]], 11
3475+ ; CHECK-NEXT: ret i1 [[V1]]
3476+ ;
3477+ entry:
3478+ %v0 = add nuw i32 %arg0 , 7
3479+ %v1 = icmp ugt i32 %v0 , 18
3480+ ret i1 %v1
3481+ }
3482+
3483+ define i1 @icmp_partial_negative_samesign_ult_to_slt (i8 range(i8 -1 , 5 ) %x ) {
3484+ ; CHECK-LABEL: @icmp_partial_negative_samesign_ult_to_slt(
3485+ ; CHECK-NEXT: entry:
3486+ ; CHECK-NEXT: [[ADD:%.*]] = add nsw i8 [[X:%.*]], -5
3487+ ; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ult i8 [[ADD]], -3
3488+ ; CHECK-NEXT: ret i1 [[CMP]]
3489+ ;
3490+ entry:
3491+ %add = add nsw i8 %x , -5
3492+ %cmp = icmp samesign ult i8 %add , -3
3493+ ret i1 %cmp
3494+ }
3495+
3496+ define i1 @icmp_pos_samesign_slt_to_ult (i8 range(i8 1 , 5 ) %x ) {
3497+ ; CHECK-LABEL: @icmp_pos_samesign_slt_to_ult(
3498+ ; CHECK-NEXT: entry:
3499+ ; CHECK-NEXT: [[CMP:%.*]] = icmp samesign ult i8 [[X:%.*]], 2
3500+ ; CHECK-NEXT: ret i1 [[CMP]]
3501+ ;
3502+ entry:
3503+ %add = add nsw i8 %x , 1
3504+ %cmp = icmp samesign slt i8 %add , 3
3505+ ret i1 %cmp
3506+ }
3507+
3508+ ; Since higher priority is given to unsigned predicates, the predicate should
3509+ ; not change
3510+ define i1 @icmp_nuw_nsw_samesign (i32 %arg0 ) {
3511+ ; CHECK-LABEL: @icmp_nuw_nsw_samesign(
3512+ ; CHECK-NEXT: entry:
3513+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ARG0:%.*]], 9
3514+ ; CHECK-NEXT: ret i1 [[CMP]]
3515+ ;
3516+ entry:
3517+ %v0 = add nuw nsw i32 %arg0 , 1
3518+ %cmp = icmp samesign ult i32 %v0 , 10
3519+ ret i1 %cmp
3520+ }
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